The present invention relates to a semiconductor device and a method of manufacturing it, and more specifically, to a structure of a semiconductor device having a stacked type capacitor and a manufacturing method thereof.
In the semiconductor device such as a dynamic random access memory (DRAM), as an integration level is increased, a chip area inevitably increases. To prevent the increase of a chip area, it is necessary to reduce the size of an individual memory cell. On the other hand, to obtain stable operation of the DRAM, it is necessary for a memory cell capacitor to maintain a capacitance of 20 fF to 30 fF. This value has not been changed even if the generation of DRAM takes turns. To satisfy contradicted requirements mentioned above, conventionally employed are capacitors have three dimensional structure such as a trench type or a stacked type.
A large scale DRAM having an integration level as high as a gigabit order is not sufficiently attained only by use of the three dimensional capacitor. Therefore, use of a dielectric film having a high dielectric constant, such as a barium strontium titanate ((Ba, Sr) TiO.sub.3) film is required as the capacitor dielectric film,
FIG. 1 shows a sectional structure of a conventional stacked type DRAM memory cell employing the (Ba, Sr) TiO.sub.3 film as the dielectric film for a capacitor.
The DRAM memory cell comprises a silicon substrate 1, trench isolation 2, a gate electrode 3 of an MOS transistor for charging and discharging capacitor, a word line 4, a source region 5 and a drain region 6 of an MOS transistor, a contact region 6a for connecting a bit line and a silicon substrate, an insulating film 7 surrounding the gate and the word line, a polysilicon plug 10 for connecting the source region 5 of the MOS transistor to a storage node electrode 19, a polysilicon plug 11 for connecting the substrate to the bit line, and an insulating film 17 for isolating the MOS transistor from the capacitor.
A conventionally-employed process of manufacturing the stacked type capacitor (shown in FIG. 1) employing the (Ba, Sr) TiO.sub.3 as the dielectric film is as follows:
A contact hole is formed through the insulating film 17. Subsequently, a Ru film is deposited on the polysilicon plug 10 by a sputtering method and then subjected to patterning by conventionally-employed reactive ion etching (RIE) using SiO.sub.2 as an etching mask. As a result, the storage node electrode 19 is obtained.
On the patterned storage node electrode 19, a (Ba, Sr) TiO.sub.3 thin film 21 is deposited by metal organic chemical vapor deposition (MOCVD). Subsequently, a plate electrode 22 is formed of a Ru film on the (Ba, Sr) TiO.sub.2 thin film 21 by sputtering. In this manner, a stacked-type capacitor is accomplished.
In the conventionally-employed manufacturing process for the stacked-type capacitor mentioned above, the SiO.sub.2 film is first patterned on the Ru film by use of lithography in the form of an island. Then, the Ru film is etched by RIE using the SiO.sub.2 film as a mask, to form the storage node electrode 19.
The size of a gap (proximity gap) between adjacent island-form SiO.sub.2 mask pieces formed herein is defined by a resolution limit of lithography, so that the proximity gap between the Ru film pieces isolated by etching cannot fall within the size of the proximity gap of the SiO.sub.2 mask.
Conventionally, it is not always easy to etch the Ru film. To isolate the Ru film completely, the Ru film must be over-etched up to the peripheral region under the SiO.sub.2 mask. For this reason, the gap between adjacent storage node electrodes formed of the Ru film becomes inevitably larger than the proximity gap of the SiO.sub.2 mask defined by a lithographic resolution limit.
When the Ru film is etched by the RIE method, the side wall of the Ru film is formed nearly vertically. To improve step coverage of the (Ba, Sr) TiO.sub.3 thin film 21, the (Ba, Sr) TiO.sub.3 thin film must be formed by a CVD (chemical vapor deposition) method or an MOCVD method even if the deposition method has a problem in forming a film uniformly.
As described in the forgoing, there are many problems in the semiconductor device comprising the conventional stack-type capacitor and in the manufacturing method thereof. First, the number of manufacturing steps increases since the Ru film is etched by RIE using the SiO.sub.2 mask in two steps. Second, the storage capacity of the capacitor cannot be increased, since the proximity gap between the storage node electrodes made of the Ru film cannot be formed within the predetermined value defined by the lithographic resolution limit. Third, step coverage of the (Ba, Sr) TiO.sub.3 thin film is poor, since the side wall of the Ru film is formed nearly vertically.